1. Field of the Invention
The present invention relates to a testing device for making a functional test on a semiconductor memory which is a logic integrated circuit including a plurality of RAMs, a plurality of ROMS and the like.
2. Background of the Invention
{First Prior Art}
FIG. 22 is a circuit diagram showing a scan register 414a of a two-phase clock system semiconductor memory testing device according to first prior art which is disclosed in U.S. Pat. No. 4,926,424, for example. Referring to FIG. 22, numerals 401a and 401b denote latch circuits, numeral 402 denotes a selector circuit, numeral 408 denotes a selector control terminal, numeral 409 denotes a serial input terminal, numeral 410 denotes a parallel input terminal, numeral 411 denotes a parallel output terminal, and numeral 412 denotes a serial output terminal. Numerals 415 and 416 denote two-phase clock system clock terminals, numeral 419 denotes an exclusive NOR circuit (hereinafter referred to as an Ex.NOR circuit), numeral 420 denotes a NOR circuit, numeral 421 denotes an OR circuit, and numeral 422 denotes a test clock terminal.
The operation is now described. When the test clock terminal 422 is fixed at a high level, an output of the NOR circuit 420 goes low and hence the OR circuit 421 transmits the level of the clock terminal 415 to an enable terminal EN of the latch circuit 401a as such. In this case, therefore, it is possible to transmit data supplied to the serial input terminal 409 or the parallel input terminal 410 to the serial and parallel output terminals 412 and 411 by supplying two-phase clock signals to the clock terminals 415 and 416.
In a read test of a tested circuit such as a RAM, on the other hand, expected data are set in the latch circuits 401a and 401b and a clock signal is supplied to the test clock terminal 422 in this state, so that data of the parallel input terminal 410 is latched by the latch circuit 401a and the content of the latch circuit 401a is inverted only when the data of the parallel input terminal 410 is different from the expected data.
Namely, when data which is different from the expected data is read from the tested circuit such as a RAM and applied to the parallel input terminal 410, the latch circuit 401a latches the data which is different from the expected data, whereby it is possible to recognize that the tested circuit such as a RAM is abnormal from the data latched in the latch circuit 401a.
FIG. 23 is a block diagram showing a scan path which is formed by the scan registers 414a shown in FIG. 23.
{Second Prior Art}
FIG. 57 shows a semiconductor memory testing device according to second prior art (refer to Japanese Patent Laying-Open No. 62-195572 (1987) and U.S. Pat. No. 4,813,043). The second prior art employs a pseudo-random number (pseudo-random series) generating algorithmic pattern generation circuit (linear feedback shift register circuit: hereinafter referred to as an LFSR circuit) as such a testing device. Referring to FIG. 57, numeral 501 denotes a base data register for storing reference data, numeral 502 denotes a constant register for supplying constants for making constant operations, numeral 503 denotes an arithmetic and logic unit (ALU) provided with a shift-in function for carrying out various arithmetic and logic operations, numeral 504 denotes a selector for selecting the input of the ALU 503, numeral 505 denotes an ALU output register for holding the operation results of the ALU 503, numeral 506 denotes a bit selection register, numeral 507 denotes an AND operation circuit, and numeral 508 denotes a parity detector.
FIG. 58 is a logic circuit diaoram showing an exemplary 4-bit LFSR circuit. Referring to FIG. 58, numeral 509 denotes an exclusive OR (Ex.OR) circuit, numerals 510, 511, 512 and 513 denote flip-flop circuits, and symbol CLK denotes a clock signal input terminal respectively. The exclusive OR circuit 509 corresponds to the parity detector 508 shown in FIG. 57, while the flip-flop circuits 510, 511, 512 and 513 correspond to the ALU output register 505 shown in FIG. 57. Referring to FIG. 58, two flip-flops 510 and 513 make inputs in the exclusive OR circuit 509, in correspondence to selection of 1001 (binary system) with respect to the bit selection register 506 shown in FIG. 57.
In the LFSR circuit according to the second prior art having the aforementioned structure, parity detection is made with respect to an arbitrary bit group of the ALU output register 505 so that the result of the detection is shifted in the ALU 503 simultaneously with an operation in the ALU 503 to update the ALU output register 505, thereby generating a complicated pattern of pseudo-random numbers at a high speed. The LFSR circuit of the second prior art generates 2.sup.n pseudo-random numbers (pseudo-random series) as an algorithmic pattern for a functional test.
Description is made on an operation in a case of employing the LFSR circuit of the second prior art as an address generation circuit with employment of full cyclic system test data for addressing a plurality of RAMs with reference to FIG. 59. FIG. 59 illustrates an address input system. Referring to FIG. 59, numerals 521a to 521c denote RAMs numerals 522a to 522c denote shift registers for selecting addresses of the respective RAMs 521a to 521c in a functional test of the RAMs 521a to 521c, numeral 523 denotes a test pattern generation circuit including the LFSR circuit (address generation circuit) of the second prior art, and symbol SIA denotes a common wire for transmitting addressing data to all shift registers 522a to 522c. As shown in FIG. 59, the plurality of RAMs 521a to 521c are connected to the single test pattern generation circuit 523. Symbols A0 to A4 denote address input terminals of the RAMs 521a to 521c, which have four, five and four input terminals respectively.
In a functional test of the RAMs 521a to 521c, the test pattern generation circuit 523 first outputs addressing data to the common wire SIA. The shift registers 522a to 522c which are connected to the common wire SIA in common are shifted in by the addressing data as transmitted, to select addresses of the RAMs 521a to 521c.
The test pattern generation circuit 523 generates quaternary full cyclic series for the RAMs 521a and 521c each having four address input terminals A0 to A3, thereby addressing the RAMs 521a and 521c on the basis thereof. Similarly, the test pattern generation circuit 523 generates quintic full cyclic series for the RAM 521b having five address input terminals A0 to A4, thereby addressing the RAM 521b on the basis thereof.
{Third Prior Art}
A semiconductor memory testing device according to third prior art is adapted to increment or decrement addresses by an address generation circuit. As shown in FIG. 59, a general counter serving as a separate member is connected to a test pattern generation circuit (LFSR circuit) 523 which is similar to that of the second prior art, to cancel redundant bits by linkage operations of the counter and the LFSR circuit 523.
{Fourth Prior Art}
FIG. 132 shows a semiconductor memory testing device according to fourth prior art. Semiconductor memories (RAM 1, RAM 2 and RAM 3) shown in FIG. 132 have data output scan paths DO (scan FFs provided with data compression functions) respectively, so that an output from the scan path DO of a preceding semiconductor memory is inputted in that of a subsequent semiconductor memory. Test results are made by shift operations of the respective scan paths DO. In order to compress data for testing with respect to the respective semiconductor memories, SINH signals (shift inhibiting signals) are inputted to inhibit shift operations of the scan paths DO.
{Fifth Prior Art}
FIGS. 157 and 158 show a conventional redundancy circuit. The redundancy circuit has a plurality of signal lines L1 to L4 which are connected to a plurality of memory cells C, a decoder (not shown) which is connected to the signal lines L1 to L4, and at least one extra signal line L5 which is connected to the memory cells C. In FIGS. 157 and 158, indicated generally at D1 to D4 are driver circuits which are connected to the decoder.
Indicated generally at S is a switch part, and switching elements disposed in the switch part are indicated at S1 to S4. Transistors are typically used as the switching elements S1 to S4. When there is a failure in the first signal line L1 of the signal lines L1 to L4, the first switching element S1 disconnects the driver circuit D1 from the first signal line L1 and connects the driver circuit D1, which is originally connected to the first signal line L1, to the second signal line L2. When there is a failure in the second signal line L2 of the signal lines L1 to L4, the second switching element S2 disconnects the driver circuit D2 from the second signal line L2 and connects the driver circuit D2, which is originally connected to the second signal line L2, to the third signal line L3. Similarly, when there is a failure in the third signal line L3 of the signal lines L1 to L4, the third switching element S3 disconnects the driver circuit D3 from the third signal line L3 and connects the driver circuit D3, which is originally connected to the third signal line L3, to the fourth signal line L4. Further, the Fourth switching element connects the driver circuit D4 to the extra signal line L5.
In the conventional redundancy circuit constructed as above, any one of the signal lines L1 to L4 including a failure is disconnected by reconnecting the signal lines in such a manner that the driver circuits are connected respectively to the next signal lines including the extra signal line L5.
{Problem of First Prior Art}
In the two-phase clock system semiconductor memory testing device according to the first prior art having the aforementioned structure, it is necessary to supply the pair of clock terminals 415 and 416 with two-phase clock signals. Thus, this device disadvantageously requires a clock driver circuit which is capable of making complicated driving for supplying the pair of clock terminals 415 and 416 with high-speed two-phase clock signals, in order to test a tested circuit such as a RAM at a high speed.
{Problem of Second Prior Art}
In general, a functional test employed for testing RAMs or the like includes a march test, for example. This test is adapted to update initially stored data ("0", for example) which are initial states, to novel storage data ("1") as to all addressing data for all RAMs. In such a march test, it is necessary to specify addresses of RAMs which are objects of data renewal. While the second prior art generate 2.sup.n full cyclic series of pseudo-random numbers by the LFSR circuit of the test pattern generation circuit 523 for addressing the RAMs as hereinabove described, address numbers n of actual RAMs depend on the types of the RAMs such that the RAMs 521a and 521b shown in FIG. 59 have four and five addresses respectively, for example. Thus, word numbers 2.sup.n which are decided by combinations of binary numbers ("0" and "1") of the address numbers n also depend on the types of the RAMs. If the number of 2.sup.n -order full cyclic series generated in the LFSR circuit is smaller than an actual word number of RAMs, therefore, there are inevitably generated words which cannot be subjected to the functional test. If the number of the 2.sup.n -order full cyclic series generated in the LFSR circuit is larger than the actual word number of the RAMs, on the other hand, partial data may be forced out from the shift registers, leading to recognition of erroneous addresses. In the second prior art, therefore, the number 2.sup.n of the full cyclic series generated in the LFSR circuit must completely match with the word number of the RAMs, and hence the degree of freedom of the RAMs subjected to the functional test is limited.
Further, it is necessary to make a burn-in test (dynamic burn-in test) while moving all addresses, bits etc., in order to carry out a functional test of RAMs. When the RAMs to be subjected to the functional test are connected in a large number, however, initialization of a necessary bit line selection register etc. cannot be made in advance of formation of a test pattern since a burn-in tester cannot generate complicated control signals in general.
{Problem of Third Prior Art}
It is possible to solve the problem of mismatching of bit numbers in the second prior art by canceling, redundant bits by linkage operations of the counter and the LFSR circuit 523 in the structure of the third prior art. However, a general counter has a larger area scale as compared with the LFSR circuit 523 such that it is difficult to integrate the same in a single integrated circuit. Therefore, an address bus is drawn out to the exterior to externally mount the counter. Thus, the third prior art requires an additional area for the counter as well as a wiring mechanism for the address bus etc., leading to remarkable reduction of area efficiency.
{Problem of Fourth Prior Art}
The device according to the fourth prior art is so wired that the same SINH signal is supplied to a plurality of scan paths DO, and hence the SINH signal is regularly supplied to a plurality of semiconductor memories. Thus, it is impossible to carry out a high-speed operation by unavailable capacitances, and hence improvement in test efficiency is limited.
{Problem of Fifth Prior Art}
In the circuit of the fourth prior art, when a failure is found in the signal lines L1 to L4, the switching elements S1 to S4 are disconnected with a laser device or the like to disconnect the drivers from connection for writing or other purposes. Since a disconnecting device is large which increases a cost.